In recent years, variable resistance nonvolatile memory devices (hereinafter, referred to also simply as “nonvolatile memory devices”) having memory cells including variable resistance nonvolatile memory elements (hereinafter, referred to also simply as “variable resistance elements”) have been researched and developed. The variable resistance elements are elements having characteristics in which a resistance value reversibly changes based on electrical signals, and capable of holding data corresponding to the resistance value in a nonvolatile manner.
Commonly known is a nonvolatile memory device including a matrix of so-called 1T1R memory cells in each of which a Metal Oxide Semiconductor (MOS) transistor and a variable resistance element are connected in series to each other at a location close to a cross-point between a bit line and a word line that are arranged perpendicular to each other. In each of the 1T1R memory cells, one of two terminals of the variable resistance element is connected to the bit line and a source line, while the other terminal is connected to a drain or source of the MOS transistor. A gate of the MOS transistor is connected to the word line. The source line is arranged parallel to the bit line or the word line.
Another memory cell structure is also generally known as a nonvolatile memory device including a matrix of cross point memory cells called 1D1R memory cells in each of which a diode and a variable resistance element are connected in series to each other at a cross-point between a bit line and a word line that are arranged perpendicular to each other.
The following describes typical examples of conventional variable resistance elements (Non-Patent Reference 1 and Patent References 1 to 3).
First, Non-Patent Reference 1 discloses a nonvolatile memory including 1T1R memory cells each using a transition metal oxide as a variable resistance element. Non-Patent Reference 1 describes that a transition metal oxide film is generally an insulator, and that a resistance value of the transition metal oxide film can therefore be changed based on a pulse voltage by performing a forming to form a conducting path for switching the resistance value between a high resistance state and a low resistance state. Here, the “forming” refers to initialization of a variable resistance element. The forming is an operation for changing a variable resistance element from a state having an extremely high resistance value after manufacture of the variable resistance element to a state where a resistance value can be changed between a high resistance state and a low resistance state according to an applied pulse voltage. In other words, the forming is used to change the variable resistance element from a state after the manufacture where the variable resistance element has not yet operated as a variable resistance element to a state where the variable resistance element is capable of serving as a variable resistance element. In general, the forming is performed only once after the manufacture.
FIG. 46 is a graph plotting a dependency of a forming start voltage on a transition metal oxide film thickness which is disclosed in Non-Patent Reference 1. The graph indicates four kinds of properties, NiO, TiO2, HfO2, and ZrO2, as transition metal oxides. The forming start voltage depends on the kinds of the transition metal oxides. When a thickness of a transition metal oxide is greater, the forming start voltage is higher. Therefore, in order to decrease the forming voltage, it is preferable to select a transition metal oxide such as NiO to form a transition metal oxide film having a small thickness. Here, the “forming voltage” refers to a voltage applied to perform a forming for a variable resistance element. The “forming start voltage” refers to the lowest voltage (a forming voltage having a minimum absolute value) required to perform a forming for a variable resistance element
Moreover, FIG. 47 is a graph plotting current-voltage (I-V) m properties which indicates unipolar resistance change properties of NiO which is disclosed in Non-Patent Reference 1. When a reset voltage of approximately 0.5 V is applied to a variable resistance element having a low resistance state, the low resistance state is changed to a high resistance state. Then, when a set voltage (point A) of approximately 1.15 V is applied to the variable resistance element, the high resistance state is changed to a low resistance state. After the change to the low resistance state (at and after the point A), current restriction is executed not to flow too much current to the variable resistance element. Therefore, after the change to the low resistance state, an extreme voltage is not applied to the variable resistance element. In FIG. 47, a solid line represents resistance change hysteresis before baking of 150° C. and 300 hours, and a broken line represents resistance change hysteresis after the baking of 150° C. and 300 hours. The resistance change hysteresis is not notably changed, even if the resistance change hysteresis is repeatedly looped by changing a voltage in the case where a voltage applied to the variable resistance element is limited after the point A where a high resistance state is changed to a low resistance state. Therefore, the high resistance state and the low resistance state are achieved with stability.
Furthermore, Patent Reference 1 discloses an ion conduction nonvolatile memory device using a rare-earth oxide thin film as a variable resistance elements.
FIG. 48 is a cross-sectional view of a memory cell disclosed in Patent Reference 1.
This memory cell has the following structure. A lower electrode 2 is formed on a substrate 1 having a high electrical conductivity (a silicon substrate 1 doped with a P-type high-concentration impurity, for example). An ion source layer 3 including a metallic element as an ion source is formed on the lower electrode 2. A memory layer 4 having a relatively high resistance value is formed on the ion source layer 3. An upper electrode 6 is formed to contact the memory layer 4 through an opening in an insulation layer 5 on the memory layer 4.
Patent Reference 1 discloses CuTe, GeSbTe, AgGeTe, and the like as a material of the ion source layer 3, and discloses a rear-earth element oxide such as a gadolinium oxide as a material of the memory layer 4. A material of the lower electrode 2 and the upper electrode 6 is described as a common semiconductor line material such as TiW and TaN. Furthermore, a gadolinium oxide for the memory layer 4 is added with metallic particles such as Cu having an amount not enough to form a layer, namely, an amount enough to keep insulation properties or semi-insulation properties.
A method of writing data into the memory cell shown in FIG. 48 is as follows. When a negative voltage causing a potential of the upper electrode 6 to be lower than a potential of the lower electrode 2, a conducting path including a large amount of metallic elements is formed in the memory layer 4, or a large number of defects resulting from the metallic elements are formed in the memory layer 4. As a result, a resistance value of the memory layer 4 is decreased. On the other hand, when a positive voltage causing the potential of the upper electrode 6 to be higher than the potential of the lower electrode 2 is applied, the conducting path or the defects formed in the memory layer 4 due to the metallic elements disappear. As a result, the resistance value of the memory layer 4 is increased.
FIG. 49 is a graph plotting I-V properties changed from an initial state regarding the memory cell shown in FIG. 48. In the first loop, a relatively high negative voltage is applied to the memory cell to change a high resistance state of the initial state to a low resistance state. The voltage is assumed to be an initialization voltage Vo. Then, when a positive potential is increased, an erasing voltage Ve is applied to the memory cell to change the low resistance state to a high resistance state. Furthermore, after the first loop, a writing voltage Vr having an absolute value smaller than that of the initialization voltage Vo is applied to the memory cell to change the high resistance state to a low resistance state.
Accordingly, Patent Reference 1 discloses a technology of lowering the initialization (forming) voltage. As described above, the addition of metallic particles to the memory layer 4 forms defects in the memory layer 4. As a result, a low voltage easily allows ion of the metallic elements to start moving. Into the empty site from which ion is moved, new ion is moved from the ion source layer 3 in contact with the memory layer 4. Such ion movements continuously occur, speedily forming a conducting path. The conducting path allows an initialization (forming) operation to be performed by a low voltage. As a result, reliability of the memory cell can be maintained.
On the other hand, Patent Reference 2 discloses a method of writing multiple values into a 1T1R memory cell using a variable resistance memory element. FIG. 50 is a graph for explaining analysis of an operation point for low resistance writing (LR writing operation point analysis) based on static properties between a Metal Insulator Semiconductor (MIS) transistor and a variable resistance element in such a 1T1R cell. As shown in FIG. 50, the properties of the variable resistance element are represented by straight lines. When a voltage higher than a threshold voltage Vth for writing data to cause a low resistance state (hereinafter, referred to as “LR writing”) is applied to the variable resistance element, a high resistance state of the variable resistance element is changed to a low resistance state. Moreover, when a gate voltage VGS of the MIS transistor is sequentially changed to VG3, VG2, and then VG1 (where VG3<VG2<VG1), the properties of the MIS transistor is changed. If the gate voltage VGS of the MIS transistor is higher, more current flows and on-resistance is lower. The change of the gate voltage VGS of the MIS transistor sequentially to VG3, VG2, and then VG1 also changes the LR writing operation point sequentially to P3, P2, and then P1, so that the variable resistance element has a low resistance value corresponding to a value of current flowing at the operation point. As described above, a level of the low resistance value of the variable resistance element controls the gate voltage VGS of the MIS transistor, and thereby controls its I-V properties so as to flexibly set the I-V properties. The method can therefore be used for multivalued memories.
Patent Reference 3 discloses a method of writing multiple values to a variable resistance element. FIG. 51 is a graph plotting resistance-voltage (R-V) characteristics of a metal insulation film (magnesium oxidation film, for example) serving as the variable resistance element. FIG. 51 shows resistance change characteristics (a) causing the variable resistance element to change into a high resistance state by applying a positive voltage (hereinafter, writing to change the variable resistance element into a high resistance state is referred to as “high resistance (HR) writing”), and (b) causing the variable resistance element to change into a low resistance state by applying a negative voltage (hereinafter, writing to change the variable resistance element into a low resistance state is referred to as “low resistance (LR) writing”). Regarding application of a positive voltage, a return path differs depending on an applied voltage, after the applied voltage is increased to be equal to or higher than a critical voltage. More specifically, when a switching voltage is higher, resistance is regressed to have a higher resistance value. As described above, Patent Reference 3 discloses that a level of a high resistance value of a variable resistance element can be set to a desired high resistance value, by setting a plurality of switching voltages to control the R-V characteristics.